The present invention relates to a semiconductor integrated circuit such as a microprocessor, a semiconductor memory having a redundant circuit, or the like.
In an integrated semiconductor memory such as a mass SRAM (static RIM), a mass DRAM (dynamic RAM) or the like, there are disposed spare cells in addition to normal memory cells (normal cells) in order to relieve defective cells if any. "A 9 ns 1 Mb CMOS SRAM", ISSCC digest of Technical Papers, pp 34-35, 1989 by K. Sasaki et al. or Japanese Laid-Open Publication No. 2-21500 discloses a spare cell reading method shown in FIGS. 15 and 16.
FIG. 15 is a circuit diagram showing the arrangement of a reading circuit portion in a conventional SRAM. In the arrangement shown in FIG. 15, the memory cells are divided into two blocks, i.e., a first cell array in which n-piece first normal cells 11.1, 11.2, . . . and one first spare cell 21 are connected to a first pair of data lines 31, and a second cell array in which n-piece second normal cells 12.1, 12.2, . . . and one second spare cells 22 are connected to a second pair of data lines 32. Normal word lines 31.1, 35.2, 35.3, 35.4, . . . are disposed for selecting one of 2n-piece normal cells 11.h, 12.h (h=1 to n), and spare word lines 37.1, 37.2 are disposed for selecting one of the two spare cells 21, 22.
There is also disposed a decoder 41 for receiving an address. Connected to the decoder 41 are (i) n-piece normal global word lines 33.1, 33.2, . . . the voltage of one of which is raised to a high level in response to an input address, (ii) one spare global word line 36 of which voltage is raised to a high level simultaneously with the one normal global word line above-mentioned, and (iii) first and second block selecting lines 34a, 34b for selecting the cell arrays. In the following description, signals on the n-piece normal global word lines 33.1, 33.2, . . . are respectively designated as NGWL1, NGWL2, . . . , signals on the 2n-piece normal word lines 35.1, 35.2, 35.3, 35.4, . . . are respectively designated as NWL1, NWL2, NWL3, NWL4, . . . a signal on the spare global word line 36 is designated as SGWL, signals on the two spare word lines 37.1, 37.2 are respectively designated as SWL1, SWL2, and signals on the first and second block selecting lines 34a, 34b are designated as BLK1, BLK2.
2n-Piece AND circuits 42.1, 42.2, 42.3, 42.4, . . . are disposed for raising one of the NWLi (i=1 to 2 n) to a high level. Of these, n-piece AND circuits 42.1, 42.3, . . . corresponding to i which is an odd number, are disposed for selecting one of the n-piece first normal cells 11.1, 11.2, . . . in response to NGWLh (h=1 to n) and the BLK2. AND circuits 44.1, 44.2 are disposed for respectively raising the SWL1 and the SWL2 to high levels. One AND circuit 44.1 is adapted to select the second spare cell 22 in response to the SGWL and the BLK1, and the other AND circuit 44.2 is adapted to select the first spare cell 21 In response to the SGWL and the BLK2. More specifically, when the BLK1 becomes a high level or a logical value 1 (the BLK2 becomes a low level or a logical value 0) and information on one of the first normal cells 11.1, 11.2, . . . is read out onto the first pair of data lines 31, information on the second spare cell 22 is read out onto the second pair of data lines 32. When the BLK2 becomes equal to 1 (the BLK1 is equal to 0) and information on one of the second normal cells 12.1, 12.2, . . . is read out onto the second pair of data lines 32, information on the first spare cell 21 is read out onto the first pair of data lines 31. Information on the first pair of data lines 31 is entered into a first sense amplifier 46.1, and information on the second pair of data lines 32 is entered into a second sense amplifier 46.2.
The first spare cell 21 serves as a substitute cell for the second normal cells 12.1, 12.2, . . . and the second spare cell 22 serves as a substitute cell for the first normal cells 11.1, 11.2, . . . . A spare address comparing circuit 91 is adapted to judge whether or not a plurality of previously stored or programmed spare addresses contain an address identical with the input address. In the affirmative, it is required to select the first or second spare cell 21, 22 as a substitute cell. In the negative, the input address is called a normal address, requiring no substitute cell. To control the foregoing, the spare address comparing circuit 91 is arranged such that a redundancy judging signal SPARE on an output signal line 92 is set to 1 when a spare address is entered, and that the SPARE is set to 0 when a normal address entered. When the SPARE is equal to 0, a redundancy judging switch 93 is adapted to supply the BLK1 to the first sense amplifier 46.1 and the BLK2 to the second sense amplifier 46.2, thus activating one sense amplifier 46.1 or 46.2. On the other hand, when the SPARE is equal to 1, the redundancy judging switch 93 is adapted to supply the BLK1 to the second sense amplifier 46.2 and the BLK2 to the first sense amplifier 46.1, thus activating the other sense amplifier 46.2 or 46.1.
According to the arrangement above-mentioned, information of one of the first and second normal cells 11.h, 1.2.h (h=1 to n) is read out onto an output data-line 39 when a normal address is entered, and information of the first or second spare cell 21 or 22 is read out onto the output data line 39 when a spare address is entered. The foregoing is shown in FIG. 16. More specifically, FIG. 16 shows an example where the second normal cell 12.1 selected by the NWL2 is accessed subsequently to the access to the first normal cell 11.1 selected by the NWL1.
First, the NGWL1, the BLK1 and the SGWL are raised by the decoder 41. This causes the NWL1 to be raised to a high level through the AND circuit 42.1 to select the first normal cell 11.1. Simultaneously, the SWL1 is raised to a high level through the AND circuit 44.1 to select the second spare cell 22. At this time, when the input address is a normal address, the SPARE becomes equal to 0. Accordingly, the first sense amplifier 46.1 is activated, causing information of the first normal cell 11.1 to be read out through the first pair of data lines 31. On the other hand, when the input address given for accessing to the first normal cell 11.1, is a spare address, the SPARE becomes equal to 1. Accordingly, the second sense amplifier 46.2 is activated, so that information of the second spare cell 21 instead of the first normal cell 11.1 which is defective, is read out through the second pair of data lines 32. If the second normal cell 12.1 is defective, the first spare cell 21 is used as a substitute cell in a similar manner.
The arrangement in FIG. 15 is adapted such that, in order to read a spare cell at a high speed, one of the NGWL1, NGWL2, . . . and the SGWL are simultaneously raised to high levels before it is judged whether or not the input address is a spare address. However, only one defective cell can be relieved for each cell array, resulting in low defect-relief rate. Japanese Patent Laid-Open Publication No. 2-21500 discloses an arrangement in which a plurality of defective cells in one cell array can relieved. According to this arrangement, the memory cells are divided into, for example, four blocks (first to fourth cell arrays). It is now supposed that each cell array has n-piece normal cells and three spare cells. By using three spare global word lines and four block selecting lines, there are utilized (i) one spare cell in each of the second to fourth cell arrays as a substitute cell for the first cell array, (ii) one spare cell in each of the third, fourth and first cell arrays as a substitute cell for the second cell array, (iii) one spare cell in each of the fourth, first and second cell arrays as a substitute cell for the third cell array, and (iv) one spare cell in each of the first to third cell arrays as a substitute cell for the fourth cell array. One sense amplifier is prepared for each cell array, and all the voltages of three spare global word lines are raised to high levels simultaneously with the voltage of one of n-piece normal global word lines, regardless of the input address which is a normal address or a spare address.
According to the conventional arrangement above-mentioned in which the defect relief rate is improved, even though the input address is a normal address, it is required that each time an input address is given, there are raised, to high levels, all the voltages of a plurality of spare global word lines in addition to one of the n-piece normal global word lines. This disadvantageously increases the current consumption.
Further, it is required to dispose a plurality of block selecting lines (four lines in the arrangement above-mentioned) in each cell array. This increases the wiring area, causing the chip area to be disadvantageously increased. With an increase in the number of cells which can be relieved in one cell array, the number of block selecting lines passing in each cell array, is increased. This further increases the chip area. Further, it is required to dispose one sense amplifier for each cell array. This also increases the chip area.
When the chip area is increased as a semiconductor memory is increased in capacity, this increases the wiring length of an output signal line for transmitting a redundancy judging signal between the spare address comparing circuit and the redundancy Judging switch. This causes the wiring capacitance to be increased, thus provoking a problem of signal delay. Likewise, other conventional semiconductor integrated circuit such as a microprocessor or the like, presents such a problem of signal delay due to wiring capacitance.
Next, a specific embodiment of the redundancy judging circuit in a conventional DRAM will be described with reference to FIGS. 28 to 31.
FIG. 28 shows the conventional redundancy judging circuit. In the drawing, each of redundant address comparing circuits 311.1 to 311.N of voltage conversion type receives an input address AY and individual redundant address comparing lines 314.1 to 314.N generate outputs C.1 to C.N, respectively. An overall redundant use detecting circuit 312 receives inputs C.1 to C.N and generates an output CO. The CO is a signal indicating whether or not a plurality of spare addresses include one that is identical with the input address AY, and is used for selecting normal cells and not selecting spare cells, or alternatively, for selecting the spare cells and not selecting the normal cells. Spare generating circuits 313.1 to 313.N of voltage conversion type receive inputs C.1 to C.N, respectively, and spare lines 315.1 to 315.N generate outputs SP.1 to SP.N, which are used for selecting one spare cell to be accessed.
There are two types of redundancy judgment: One is executed by the redundant address comparing circuits 311.1. to 311.N for judging whether or not the m-bit input address AY (AY1 to AYm, XAY1 to XAYm) is identical with the spare address programmed in fuses constituting, e.g., a ROM (Read Only Memory). By way of example, FIG. 29A shows the structure of the redundant address comparing circuit 311.N. The redundant address comparing circuit 311.N is composed of a dynamic NOR circuit consisting of N-channel MOSFETs Qa1 to Qam and Qb1 to Qbm, P-channel MOSFETs Qp1 and Qq1, fuses Fa1 to Fam and Fb1 to Fbm, a driver DR1, and like component. The result of judgment by each of the redundant address comparing circuits 311.1 to 311.N is outputted as H or L, depending on the logic level of the output voltage.
The other type of redundancy judgment is executed by the overall redundant use detecting circuit 312 for judging whether or not at least one of the N-piece redundant address comparing circuits 311.1 to 311.N has received the input address AY that is identical with the spare address. FIG. 29B shows the overall redundant use detecting circuit 312 which is composed of a dynamic NOR circuit consisting of N-channel MOSFETs QC1 to QCN, P-channel MOSFETs Qp2 and Qq2, a driver DR2, and like component. The result of judgment by the overall redundant use detecting circuit 312 is also outputted as H or L, depending on the logic level of the output voltage.
The operation of the foregoing redundancy judging circuit will roughly be described with reference to FIG. 30A. If there is a change in the input address AYn, XAYn, for example, an address transition detect signal ATD composed of a low-level pulse is applied to the Qp1, so that the potential of the output C.N of the redundant address comparing circuit 311.N, for example, is changed. The voltage change is then inputted to the overall redundant use detecting circuit 312 and similarly changes the potential of the CO. In this case, a delay in operation is generated over a time Td between the change of the AYn, XAYn and the change in potential of the CO. FIG. 30B shows the relationship between the operational delay time red and the number of nodes C.1 to C.N. From the drawing, it will be appreciated that the increase of the Td is almost proportional to the increase of the N.
The C.1 to C.N are also inputted to the spare generating circuits 313.1 to 313.N, which are provided based on a one-by-one correspondence. The spare generating circuits 313.1 to 313.N are basically composed of such a circuit of drivers DR3 and DR4 connected in cascade as shown in FIG. 29C which shows, by way of example, the structure of the spare generating circuit 813.N.
FIG. 31 schematically shows the signal path in an IC chip. Memory cells on the chip are divided into a plurality of blocks. Each block comprises a memory array 330 in which the memory cells are disposed and a memory subarray 331 for controlling the access to the memory array 330. The signal path schematically shown in FIG. 31 indicates a typical on-chip arrangement of a redundant address comparing circuit 311 (representative of the N-piece redundant address comparing circuits 311.1 to 311.N), a spare generating circuit 313 (representative of the N-piece spare generating circuits 313.1 to 313.N), and the overall redundant use detecting circuit 312. It also indicates the process in which the memory cells in each block are accessed. The spare cells are selected by a combination of the output SP of the spare generating circuit 313 and a signal BLK, which is one of a plurality of block select signals.
As the capacity of a memory is increased, its signal path is also increased. For example, the signal path of a 64 M-bit DRAM exceeds 12 mm. The output SP of the spare generating circuit 313 disposed in the center of the chip, e.g., is transmitted along the signal line having a length of 12 mm so that, upon reaching the memory subarray 331, it is selected by a transfer gate control in response to the block select signal BLK, thereby eventually enabling an access to an objective memory cell.
Meanwhile, however, the output SP of the spare generating circuit 313 is significantly delayed due to the delay resulting from wiring, with the result that the operation of the spare line is also delayed and hence the access to the spare cells is delayed. The situation is the same with the output CO of the overall redundant use detecting circuit 312. If the generation of an inhibition signal or activation signal to a normal line is delayed, there arises either of the following problems: If the inhibition signal is delayed, both normal line, which is not inhibited only temporarily, and spare line may be selected simultaneously, resulting in a lower-speed reading operation. On the other hand, if the activation signal is delayed, the reading out of a memory cell may be delayed accordingly. Each problem is disadvantageous for providing a higher-speed reading operation.
The redundancy Judging circuit also has a factor of inhibiting a high-speed access to the memory cells. In the conventional embodiment, since the dynamic NOR circuit shown in FIG. 29A compares the input address with the spare address programmed in the fuse to judge whether or not the former address is identical with the latter, the floating capacitance of the node of the output C.N increases as more fuses are used in accordance with, e.g., the enhancement of the storage capacity. As a result, the operation of the dynamic NOR circuit becomes slower, as shown-in FIG. 30B. In other words, the time required for charging the node of the output C.N by means of the P-channel MOSFET Qp1 of FIG. 29A is disadvantageously increased. The situation is the same with the nodes of the other outputs C.1 to C.(N-1).
The output voltage of the dynamic NOR circuit, which constitutes the redundant address comparing circuit 311, is inputted to the other dynamic NOR circuit constituting the overall redundant use detecting circuit 312 shown in FIG. 29B. Consequently, if the generation of the output voltage of the redundant address comparing circuit 313 is delayed, the generation of the output CO of the overall redundant use detecting circuit 312 is delayed accordingly. Moreover, the time required for charging the node CO by means of the P-channel MOSFET Qp2 of FIG. 29B is also increased in the overall redundant use detecting circuit 312, similarly to the redundant address comparing circuit 311, resulting in the generation of a delay. Consequently, the generation of the inhibition signal to the normal line is delayed and both normal line and spare line are selected temporarily, thus disadvantageously reducing the speed of a reading operation.
If the degree of redundancy is raised, an improvement in production yield of the memory chips can be expected. However, the use of a redundant circuit incurs the increase of the chip size, while the number of chips obtained from one wafer is reduced. Therefore, it is impossible to mount an excessively large number of redundant circuits on a single chip. In view of the foregoing, a method of using a redundant circuit with higher efficiency has been devised in recent years (Kikukawa, et al., "Novel Flexible Redundancy Architecture for 64 Mb DRAM and Beyond", IEICE Digest of Technical Papers of Autumn Conference, vol. 5, p.152, 1992).
In a memory LSI of multi-bit configuration, in particular, the efficient use of a redundant circuit is strongly desired. Below, an embodiment of the redundant circuit used in the conventional DRAM of multi-bit configuration will be described with reference to the drawings.
FIG. 41 is a schematic view of a 4-bit DRAM using the conventional redundant circuit. In the drawings are shown a memory cell array 1 for I/O0, a memory cell array 2 for I/O1, a memory cell array 3 for I/O2, a memory cell array 4 for I/O3, a redundant cell array 5 for I/O0, a redundant cell array 6 for I/O1, a redundant cell array 7 for I/O2, and a redundant cell array 8 for I/O3. There are also shown a column predecoder 11, a column address bus 12, a column predecode signal bus 13, column decoders 14 to 17, column decode signals 18 to 21, redundant fuse circuits 22 to 29 for column addresses, redundant signal lines 30 to 37, an intermediate amp 38 for I/O0, an intermediate amp 39 for I/O1, an intermediate amp 40 for I/O2, an intermediate amp 41 for I/O3, pairs of data lines 42 to 45 from the memory cell arrays to the intermediate amps in the I/O's, pairs of data lines 46 to 49 from the intermediate amps to the output circuits (not shown) in the I/O's, column switches 50 to 89, column switches 91 to 98 for the redundant cell arrays, redundant column decoders 191 to 194, and redundant column decode signals 195 to 198.
FIG. 42 is a schematic view of the contents of the memory cell arrays 1 to 4 in FIG. 41. FIG. 43 is a specific circuit diagram of the redundant fuse circuits 22 to 29 in FIG. 41. In FIG. 42 are shown word lines 101 to 105, a memory cell 106, sense amps 107 to 111, a pair of data lines 112 from the memory cell array to the intermediate amp, N-channel MOSFETs 113 to 122, bit lines 123 to 132, column decode signal lines 133 to 137, and column switches 138 to 142. In FIG. 43 are shown a redundant fuse precharge signal input terminal 150, a first power supply 151. P-channel MOSFETs 152 and 153, an inverter 154, a redundancy detect signal output terminal 155, address input terminals 156 to 161, N-channel MOSFETs 162 to 167, fuse elements 168 to 173, and an internal node 174.
Below, the operation of the conventional DRAM of multi-bit configuration thus constituted will be described. In FIG. 41, the memory cell arrays 1 to 4 are first activated so that data is read out of the memory cells to be amplified. In the individual I/O's, the amplified data is read out onto the pairs of data lines 42 to 45 via the column switches 50 to 89, further amplified by the intermediate amps 38 to 41, and then transferred to the output circuit along the pairs of data lines 46 to 49. At this stage, one out of the column switches 50 to 89 is selected in each I/O in response to one of the column decode signals 18 to 21 driven by the column decoders 14 to 17, respectively. The column switches are individually connected to the bit lines, as shown in FIG. 42, so that the data on the bit line of the selected column address is read out onto the pair of data lines. The selection with the column address is carried out by predecoding the column address inputted via the column address bus 12 in the predecode circuit 11 and transmitting its output signal to the column decoders 14 to 17 via the column predecode signal bus 13.
If the address inputted is under redundant relief, any of the redundant fuses 22 to 29 judges that the inputted address is a redundant address and outputs a redundant address detect signal to any of the redundant signal lines 30 to 37. If the redundant address detect signal is outputted onto the redundant signal line 30, e.g., it follows that the redundant address detect signal Is for I/O0. Consequently, the redundant column decoder 191 for I/O0 is operated so as to output the redundant column decode signal 195, thereby reading data out of the redundant cell array 5 onto the pair of data lines 42 via the redundant column switch 91 or 92. When the redundant address detect signal is outputted onto the redundant signal line 30, the operation of the column decoder 14 is stopped, and hence the reading of data out of the memory cell array 1 is also stopped, thereby preventing a mis-operation resulting from the collision of data on the pair of data lines 42. Meanwhile, the I/O1 to I/O3 are normally operated. FIG. 44 is a timing chart showing the foregoing operation. The redundant fuses 22 to 29 are such circuits for judging redundant addresses as shown in FIG. 43, in which, of the address input terminals 156 to 161, each even-numbered terminal and its adjacent odd-numbered terminal form a pair to which complementary signals indicating the address are inputted. If the inputted address matches the address programmed in the fuse elements 168 to 173 (the state in which the fuses are disconnected and hence the electric charge of the node 174 is not removed by the ground), the output of the circuit generates "H", which will serve as the redundant address detect signal indicating the redundant address.
In general, as the bit width of a memory of multi-bit configuration is increased, the column address thereof is degenerated accordingly. Since the present conventional embodiment is of 4-bit configuration, the lower 2 bits of its column addresses are degenerated, compared with a chip of 1-bit configuration. The blocks divided in the degenerate lower 2 bits correspond to the I/O0 to I/O3, and the memory cell arrays are isolated corresponding to the 1/00 to 1/03. The memory thus constituted is not supplied with a signal for distinguishing the I/O0 to I/O3 from outside the chip, so that it becomes necessary to provide each I/O with the redundant cell array. As for the redundant fuse, it is desirable to individually perform redundant relief with respect to each I/O in order to improve the relief efficiency. For this purpose, however, the redundant fuse circuit must be disposed in each I/O as shown in FIG. 41, for the redundant fuse circuit only has the function of judging a redundant address.
In the conventional memory of multi-bit configuration shown in FIG. 41, therefore, the area occupied by the redundant circuits increases as the number of the I/O's increases, since it is necessary to provide each I/O with the redundant circuit, resulting in an increase in the chip size. Since the redundant circuit, especially redundant fuse circuit, requires a large area, an increase in number of the redundant circuits presents a serious problem. An increase in the chip area reduces the number of chips obtained from one wafer, resulting In the reduction of the production yield, which renders the provision of the redundant circuits ineffective.
In a memory LSI provided with a serial port, the lowering of the operating speed due to the use of the redundant circuits has become a problem, and a method of improving the situation has been devised (Miyauchi, et al., "4 Mb Field Memory", IEICE Digest of Technical Papers ICD90-112, pp. 45-49, 1990).
Below, an embodiment of the redundant circuit of a conventional memory being provided with a serial port will be described with reference to the drawings.
FIG. 60 is a schematic view of the conventional memory being provided with a serial port using the redundant circuits. In the drawing are shown a P/S circuit (parallel to serial converting circuit) 101 for a normal memory cell array, a P/S circuit 102 for a redundant memory cell array, a normal memory cell array 103, a redundant memory cell array 104, and a serial data bus 105.
Below, the operation of the conventional memory with a serial port thus constituted will be described. In FIG. 60, the memory cell array 103 is first activated so that data is read out of the memory cell to be amplified by the amplifier circuit. The amplified data is transferred to the P/S circuit 101, where the data is subjected to a P/S conversion, so as to be transferred to an output circuit via the serial data bus 105. If the selected address contains a failed memory cell, the redundant memory cell array 104 is activated, so that correct data is outputted from the P/S circuit for a redundant memory cell to the serial data bus 105.
FIG. 61 is a view diagrammatically showing the foregoing operation, in which are shown a redundant memory cell 901, a P/S circuit 902 for redundant data, a serial data bus 903, a P/S circuit 904 for normal memory cell array, a parallel data bus 905, and a normal memory cell 906. In the drawing, .smallcircle. and designate normal data and faulty data, respectively. In FIG. 61, it is assumed that the faulty data is read out into the P/S circuit 904 for a normal memory cell array via the parallel data bus 905 (the faulty data is the sixth one from left). The normal P/S circuit 904 performs a P/S conversion by sequentially reading data onto the serial data bus 903. However, since the sixth data from left is faulty, it is required to read correct data out of the P/S circuit for redundant data 902 to the serial data bus 903 exactly when the sixth data is supposed to be read out.
In the conventional memory thus constituted, the replacement by redundant data is performed on the serial data bus which transfers data at a high speed. However, the constitution is disadvantageous in that it cannot operate properly if serial output is to be implemented at a higher speed.